1. Technical Field
The disclosure relates to a layout decomposition method and method for manufacturing a semiconductor device applying the same.
2. Description of the Related Art
With a continuing development of reduce-sized electrical devices, the features such as integrated circuits (ICs) thereon are being made smaller and smaller. The fine pitches and patterns of features are required to satisfy the demands of the smaller devices. However, the required fine pitches and patterns of features raise the difficulty of the device fabrication. The feature size reduction could be limited due to the conventional processing techniques; for example, photolithography techniques have a minimum pitch below which features cannot be formed reliably. Generally, the ability to project an accurate image of increasingly smaller features onto the substrate/wafer is limited by the wavelength of the light used in photolithography, and the ability of the lens system. The yield of the photolithographic process gradually decreases, and its cost increases, as k1, a dimensionless coefficient of process-related factor, decreases below 0.35. Reducing k1 below 0.28 for a single exposure is not practical. Typically, double exposure is adopted for forming the features containing fine patterns and large patterns on a device.
Also, the “pitch doubling” technique has been proposed for extending the capabilities of photolithographic techniques beyond their minimum pitch, and it allows the number of features in a region of the substrate to be doubled. However, the doubled features formed by the “pitch doubling” technique would cause the problem to the areas requiring forming the odd-numbered features.